{"doi":"10.1145/2678277","title":"Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance","abstract":"<jats:p>Superscalar in-order processors form an interesting alternative to out-of-order processors because of their energy efficiency and lower design complexity. However, despite the reduced design complexity, it is nontrivial to get performance estimates or insight in the application--microarchitecture interaction without running slow, detailed cycle-level simulations, because performance highly depends on the order of instructions within the application’s dynamic instruction stream, as in-order processors stall on interinstruction dependences and functional unit contention. To limit the number of detailed cycle-level simulations needed during design space exploration, we propose a mechanistic analytical performance model that is built from understanding the internal mechanisms of the processor.</jats:p>\n          <jats:p>The mechanistic performance model for superscalar in-order processors is shown to be accurate with an average performance prediction error of 3.2% compared to detailed cycle-accurate simulation using gem5. We also validate the model against hardware, using the ARM Cortex-A8 processor and show that it is accurate within 10% on average. We further demonstrate the usefulness of the model through three case studies: (1) design space exploration, identifying the optimum number of functional units for achieving a given performance target; (2) program--machine interactions, providing insight into microarchitecture bottlenecks; and (3) compiler--architecture interactions, visualizing the impact of compiler optimizations on performance.</jats:p>","journal":"ACM Transactions on Architecture and Code Optimization","year":2015,"id":690004,"datarank":0.4636563680037475,"base_score":3.091042453358316,"endowment":3.091042453358316,"self_citation_contribution":0.4636563680037475,"citation_network_contribution":0.0,"self_endowment_contribution":0.4636563680037475,"citer_contribution":0.0,"corpus_percentile":null,"corpus_rank":null,"citation_count":21,"citer_count":0,"citers_with_citation_signal":0,"citers_with_endowment":0,"datacite_reuse_total":0,"is_dataset":false,"is_dataset_confidence":null,"is_data_producer":false,"deposit_databanks":null,"is_oa":false,"file_count":0,"downloads":0,"has_version_chain":false,"published_date":null,"fair_score":null,"fair_percentile":null,"algorithm_id":"datarank_citation_only_1hop_v6","ranking_scope":"data_only","authors":[{"id":1802609,"name":"Stijn Eyerman","orcid":null,"position":1,"is_corresponding":false},{"id":1542261,"name":"Lieven Eeckhout","orcid":null,"position":2,"is_corresponding":false},{"id":1802608,"name":"Maximilien B. Breughe","orcid":null,"position":0,"is_corresponding":false}],"reference_count":0,"raw_metadata":{"has_enrichment":true,"resolved":true,"title":"Mechanistic Analytical Modeling of Superscalar In-Order Processor Performance","abstract":"<jats:p>Superscalar in-order processors form an interesting alternative to out-of-order processors because of their energy efficiency and lower design complexity. However, despite the reduced design complexity, it is nontrivial to get performance estimates or insight in the application--microarchitecture interaction without running slow, detailed cycle-level simulations, because performance highly depends on the order of instructions within the application’s dynamic instruction stream, as in-order processors stall on interinstruction dependences and functional unit contention. To limit the number of detailed cycle-level simulations needed during design space exploration, we propose a mechanistic analytical performance model that is built from understanding the internal mechanisms of the processor.</jats:p>\n          <jats:p>The mechanistic performance model for superscalar in-order processors is shown to be accurate with an average performance prediction error of 3.2% compared to detailed cycle-accurate simulation using gem5. We also validate the model against hardware, using the ARM Cortex-A8 processor and show that it is accurate within 10% on average. We further demonstrate the usefulness of the model through three case studies: (1) design space exploration, identifying the optimum number of functional units for achieving a given performance target; (2) program--machine interactions, providing insight into microarchitecture bottlenecks; and (3) compiler--architecture interactions, visualizing the impact of compiler optimizations on performance.</jats:p>","is_dataset_classified":null,"base_score":3.091042453358316,"endowment":3.091042453358316,"datacite_reuse_total":0,"file_count":0,"downloads":0,"views":0,"has_version_chain":false,"is_dataset":false,"is_oa":false,"pmid":"21097893","pmcid":null,"openalex_id":"https://openalex.org/W2087838646","authors":[],"funders":[{"funder_name":"European Research Council under the European Community's Seventh Framework Programme (FP7/2007-2013)/ERC","grant_id":"259295","title":"Dependable Performance on Many-Thread Processors"}],"total_grants":1,"fwci":3.5483,"citation_percentile":0.92801988,"influential_citations":0,"citation_trend":[{"year":2015,"count":2},{"year":2016,"count":2},{"year":2017,"count":2},{"year":2018,"count":5},{"year":2019,"count":1},{"year":2020,"count":4},{"year":2021,"count":1},{"year":2022,"count":1},{"year":2023,"count":1},{"year":2025,"count":2}],"oa_status":"bronze","license":"https://www.acm.org/publications/policies/copyright_policy#Background","oa_locations":[{"url":"https://dl.acm.org/doi/pdf/10.1145/2678277","host_type":"journal"},{"url":"https://dl.acm.org/doi/pdf/10.1145/2678277","host_type":"publisher"},{"url":"https://dl.acm.org/doi/10.1145/2678277","host_type":"publisher"},{"url":"https://doi.org/10.1145/2678277","host_type":"journal"},{"url":"http://hdl.handle.net/1854/LU-5823684","host_type":"repository"},{"url":"http://citeseerx.ist.psu.edu/viewdoc/summary?doi=10.1.1.720.3819","host_type":""},{"url":"https://biblio.ugent.be/publication/5823684/file/5823732.pdf","host_type":"repository"},{"url":"http://dl.acm.org/ft_gateway.cfm?id=2678277&type=pdf","host_type":""},{"url":"https://dx.doi.org/10.1145/2678277","host_type":""},{"url":"http://doi.org/10.1145/2678277","host_type":""},{"url":"https://biblio.ugent.be/publication/5823684","host_type":""},{"url":"https://biblio.ugent.be/publication/5823684/file/5823732","host_type":""},{"url":"http://dx.doi.org/10.1145/2678277","host_type":""}],"fields_of_study":["Parallel Computing and Optimization Techniques","Low-power high-performance VLSI design","Ferroelectric and Negative Capacitance Devices","02 engineering and technology","01 natural sciences","0103 physical sciences","0202 electrical engineering, electronic engineering, information engineering"],"mesh_terms":[],"keywords":["Computer science","Superscalar","Microarchitecture","Design space exploration","Out-of-order execution","Compiler","Parallel computing","Speculative execution","Computer architecture","Embedded system","Operating system","cycle stacks","Measurement","Technology and Engineering","Design","Performance","processor design space exploration","functional units","performance modeling","inter-instruction dependences","MICROPROCESSOR","SIMULATION","PARALLELISM","Superscalar in-order processors","Experimentation","THROUGHPUT MODEL"],"sdg_mappings":[{"sdg_number":7,"sdg_label":"7. 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