{"doi":"10.1109/uksim.2010.100","title":"A Simulation of Cache Sub-banking and Block Buffering as Power Reduction Techniques for Multiprocessor Cache Design","abstract":null,"journal":"2010 12th International Conference on Computer Modelling and Simulation","year":2010,"id":18882,"datarank":0.2528048031894078,"base_score":1.0986122886681096,"endowment":1.0986122886681096,"self_citation_contribution":0.16479184330021646,"citation_network_contribution":0.08801295988919135,"self_endowment_contribution":0.16479184330021646,"citer_contribution":0.08801295988919135,"corpus_percentile":null,"corpus_rank":null,"citation_count":2,"citer_count":2,"citers_with_citation_signal":2,"citers_with_endowment":2,"datacite_reuse_total":0,"is_dataset":false,"is_dataset_confidence":null,"is_data_producer":false,"deposit_databanks":null,"is_oa":false,"file_count":0,"downloads":0,"has_version_chain":false,"published_date":null,"fair_score":null,"fair_percentile":null,"algorithm_id":"datarank_citation_only_1hop_v6","ranking_scope":"data_only","authors":[{"id":129678,"name":"Anastacia Alvarez","orcid":null,"position":1,"is_corresponding":false},{"id":129679,"name":"Joy Alinda Reyes","orcid":null,"position":2,"is_corresponding":false},{"id":129677,"name":"Jestoni V. Zarsuela","orcid":null,"position":0,"is_corresponding":false}],"reference_count":0,"raw_metadata":{"has_enrichment":true,"base_score":1.0986122886681096,"endowment":1.0986122886681096,"datacite_reuse_total":0,"file_count":0,"downloads":0,"views":0,"has_version_chain":false,"is_dataset":false,"is_oa":false,"pmid":"21071399","pmcid":null,"openalex_id":"https://openalex.org/W1989229381","authors":[],"funders":[],"total_grants":0,"fwci":0.4994,"citation_percentile":0.64681507,"influential_citations":0,"citation_trend":[],"oa_status":"closed","license":null,"oa_locations":[{"url":"http://xplorestaging.ieee.org/ielx5/5479086/5480262/05480502.pdf?arnumber=5480502","host_type":"publisher"},{"url":"https://doi.org/10.1109/uksim.2010.100","host_type":""}],"fields_of_study":["Parallel Computing and Optimization Techniques","Low-power high-performance VLSI design","Interconnection Networks and Systems","Computer Science","Engineering"],"mesh_terms":[],"keywords":["Cache","Computer science","Cache pollution","Cache algorithms","Cache coloring","Smart Cache","Cache invalidation","Page cache","Parallel computing","MESI protocol","CPU cache","Operating system","Embedded system"],"sdg_mappings":[{"sdg_number":0,"sdg_label":"Affordable and clean energy"}],"linked_datasets":[],"clinical_trials":[],"software_tools":[],"database_accessions":[],"source":"live","citation_network_status":"fetched"},"created_at":"2026-06-04T00:14:08.698154Z","pmid":null,"pmcid":null,"fwci":null,"citation_percentile":null,"influential_citations":0,"oa_status":null,"license":null,"views":0,"total_file_size_bytes":0,"version_count":0,"fair_f":null,"fair_a":null,"fair_i":null,"fair_r":null,"fair_zscore":null,"fair_rationale":null,"fair_model":null,"fair_agent_version":null,"fair_fulltext_source":null,"fair_has_llm":null,"fair_computed_at":null,"clinical_trials":[],"software_tools":[],"db_accessions":[],"linked_datasets":[],"topics":[]}