{"doi":"10.1109/eh.2004.1310830","title":"Multi-objective optimization of a parameterized VLIW architecture","abstract":null,"journal":"Proceedings. 2004 NASA/DoD Conference on Evolvable Hardware, 2004.","year":null,"id":37652,"datarank":0.6489670773185073,"base_score":2.1972245773362196,"endowment":2.1972245773362196,"self_citation_contribution":0.32958368660043297,"citation_network_contribution":0.31938339071807437,"self_endowment_contribution":0.32958368660043297,"citer_contribution":0.31938339071807437,"corpus_percentile":null,"corpus_rank":null,"citation_count":8,"citer_count":7,"citers_with_citation_signal":6,"citers_with_endowment":6,"datacite_reuse_total":0,"is_dataset":false,"is_dataset_confidence":null,"is_data_producer":false,"deposit_databanks":null,"is_oa":false,"file_count":0,"downloads":0,"has_version_chain":false,"published_date":null,"fair_score":null,"fair_percentile":null,"algorithm_id":"datarank_citation_only_1hop_v6","ranking_scope":"data_only","authors":[{"id":168766,"name":"V. Catania","orcid":null,"position":1,"is_corresponding":false},{"id":168767,"name":"M. Palesi","orcid":null,"position":2,"is_corresponding":false},{"id":168768,"name":"D. Patti","orcid":null,"position":3,"is_corresponding":false},{"id":168765,"name":"G. Ascia","orcid":null,"position":0,"is_corresponding":false}],"reference_count":0,"raw_metadata":{"has_enrichment":true,"base_score":2.1972245773362196,"endowment":2.1972245773362196,"datacite_reuse_total":0,"file_count":0,"downloads":0,"views":0,"has_version_chain":false,"is_dataset":false,"is_oa":false,"pmid":"24523987","pmcid":null,"openalex_id":"https://openalex.org/W2163046274","authors":[],"funders":[],"total_grants":0,"fwci":0.7899,"citation_percentile":0.73652616,"influential_citations":0,"citation_trend":[{"year":2012,"count":1},{"year":2014,"count":1},{"year":2016,"count":1}],"oa_status":"closed","license":null,"oa_locations":[{"url":"https://doi.org/10.1109/eh.2004.1310830","host_type":""}],"fields_of_study":["Embedded Systems Design Techniques","VLSI and FPGA Design Techniques","Parallel Computing and Optimization Techniques","Computer Science","Engineering"],"mesh_terms":[],"keywords":["Very long instruction word","Computer science","Instruction set","Design space exploration","Instruction-level parallelism","Computer architecture","Abstraction","Parameterized complexity","Memory hierarchy","Parallel computing","Set (abstract data type)","Microarchitecture","Embedded system","Application-specific instruction-set processor","Abstraction layer","Parallelism (grammar)","Cache","Software","Operating system","Programming language"],"sdg_mappings":[{"sdg_number":0,"sdg_label":"Affordable and clean energy"}],"linked_datasets":[],"clinical_trials":[],"software_tools":[],"database_accessions":[],"source":"live","citation_network_status":"fetched"},"created_at":"2026-06-10T20:27:33.878295Z","pmid":null,"pmcid":null,"fwci":null,"citation_percentile":null,"influential_citations":0,"oa_status":null,"license":null,"views":0,"total_file_size_bytes":0,"version_count":0,"fair_f":null,"fair_a":null,"fair_i":null,"fair_r":null,"fair_zscore":null,"fair_rationale":null,"fair_model":null,"fair_agent_version":null,"fair_fulltext_source":null,"fair_has_llm":null,"fair_computed_at":null,"clinical_trials":[],"software_tools":[],"db_accessions":[],"linked_datasets":[],"topics":[]}