{"doi":"10.1109/date.2010.5456936","title":"A reconfigurable cache memory with heterogeneous banks","abstract":null,"journal":"2010 Design, Automation &amp; Test in Europe Conference &amp; Exhibition (DATE 2010)","year":2010,"id":18133,"datarank":0.7147337258934423,"base_score":2.0794415416798357,"endowment":2.0794415416798357,"self_citation_contribution":0.31191623125197543,"citation_network_contribution":0.4028174946414668,"self_endowment_contribution":0.31191623125197543,"citer_contribution":0.4028174946414668,"corpus_percentile":null,"corpus_rank":null,"citation_count":7,"citer_count":6,"citers_with_citation_signal":5,"citers_with_endowment":5,"datacite_reuse_total":0,"is_dataset":false,"is_dataset_confidence":null,"is_data_producer":false,"deposit_databanks":null,"is_oa":false,"file_count":0,"downloads":0,"has_version_chain":false,"published_date":null,"fair_score":null,"fair_percentile":null,"algorithm_id":"datarank_citation_only_1hop_v6","ranking_scope":"data_only","authors":[{"id":127176,"name":"Juan C Moure","orcid":null,"position":1,"is_corresponding":false},{"id":127177,"name":"Dolores Rexachs","orcid":null,"position":2,"is_corresponding":false},{"id":127178,"name":"Emilio Luque","orcid":null,"position":3,"is_corresponding":false},{"id":127175,"name":"Domingo Benitez","orcid":null,"position":0,"is_corresponding":false}],"reference_count":0,"raw_metadata":{"has_enrichment":true,"base_score":2.0794415416798357,"endowment":2.0794415416798357,"datacite_reuse_total":0,"file_count":0,"downloads":0,"views":0,"has_version_chain":false,"is_dataset":false,"is_oa":false,"pmid":"21071399","pmcid":null,"openalex_id":"https://openalex.org/W3140186264","authors":[],"funders":[],"total_grants":0,"fwci":0.768,"citation_percentile":0.76193609,"influential_citations":2,"citation_trend":[{"year":2012,"count":1},{"year":2013,"count":1},{"year":2016,"count":2},{"year":2017,"count":1},{"year":2021,"count":1}],"oa_status":"closed","license":null,"oa_locations":[{"url":"http://xplorestaging.ieee.org/ielx5/5450668/5456897/05456936.pdf?arnumber=5456936","host_type":"publisher"},{"url":"https://doi.org/10.1109/date.2010.5456936","host_type":""},{"url":"http://hdl.handle.net/10553/75619","host_type":"repository"}],"fields_of_study":["Parallel Computing and Optimization Techniques","Interconnection Networks and Systems","Embedded Systems Design Techniques","Computer Science","Engineering"],"mesh_terms":[],"keywords":["Cache","Cache algorithms","Computer science","Cache pollution","Cache invalidation","Cache coloring","Smart Cache","Page cache","Parallel computing","MESI protocol","Cache-oblivious algorithm","Bus sniffing","Pipeline burst cache","Embedded system","CPU cache"],"sdg_mappings":[{"sdg_number":0,"sdg_label":"Affordable and clean energy"}],"linked_datasets":[],"clinical_trials":[],"software_tools":[],"database_accessions":[],"source":"live","citation_network_status":"fetched"},"created_at":"2026-06-03T18:27:50.406567Z","pmid":null,"pmcid":null,"fwci":null,"citation_percentile":null,"influential_citations":0,"oa_status":null,"license":null,"views":0,"total_file_size_bytes":0,"version_count":0,"fair_f":null,"fair_a":null,"fair_i":null,"fair_r":null,"fair_zscore":null,"fair_rationale":null,"fair_model":null,"fair_agent_version":null,"fair_fulltext_source":null,"fair_has_llm":null,"fair_computed_at":null,"clinical_trials":[],"software_tools":[],"db_accessions":[],"linked_datasets":[],"topics":[]}