{"doi":"10.1109/acsd.2017.14","title":"Plato: A Tool for Behavioural Specification of Asynchronous Circuits","abstract":null,"journal":"2017 17th International Conference on Application of Concurrency to System Design (ACSD)","year":2017,"id":687773,"datarank":0.0,"base_score":0.0,"endowment":0.0,"self_citation_contribution":0.0,"citation_network_contribution":0.0,"self_endowment_contribution":0.0,"citer_contribution":0.0,"corpus_percentile":null,"corpus_rank":null,"citation_count":0,"citer_count":0,"citers_with_citation_signal":0,"citers_with_endowment":0,"datacite_reuse_total":0,"is_dataset":false,"is_dataset_confidence":null,"is_data_producer":false,"deposit_databanks":null,"is_oa":false,"file_count":0,"downloads":0,"has_version_chain":false,"published_date":null,"fair_score":null,"fair_percentile":null,"algorithm_id":"datarank_citation_only_1hop_v6","ranking_scope":"data_only","authors":[{"id":1796763,"name":"Jonathan Beaumont","orcid":null,"position":0,"is_corresponding":false}],"reference_count":0,"raw_metadata":{"has_enrichment":true,"resolved":true,"title":"Plato: A Tool for Behavioural Specification of Asynchronous Circuits","abstract":"Asynchronous circuits are becoming increasingly important in system design, where they orchestrate the interface between synchronous computation components and the analogue environment. However, wide adoption of asynchronous circuits by industrial users is hindered by a steep learning curve for asynchronous control models, such as Signal Transition Graphs, that are developed by the academic community for specification, verification and synthesis of asynchronous circuits. Previously, we have introduced a novel high-level description language for asynchronous circuits, which is based on behavioural concepts - high-level descriptions of asynchronous circuit requirements. In this paper we will discuss our open-source tool, PLATO which allows the specification of asynchronous circuits using concepts, and features the ability to automatically translate these to Signal Transition Graphs for further processing by conventional asynchronous EDA tools, such as PETRIFY and MPSAT.","is_dataset_classified":null,"base_score":0.0,"endowment":0.0,"datacite_reuse_total":0,"file_count":0,"downloads":0,"views":0,"has_version_chain":false,"is_dataset":false,"is_oa":false,"pmid":"26207759","pmcid":null,"openalex_id":"https://openalex.org/W2770353918","authors":[],"funders":[],"total_grants":0,"fwci":0.0,"citation_percentile":0.18229809,"influential_citations":0,"citation_trend":[],"oa_status":"closed","license":null,"oa_locations":[{"url":"http://xplorestaging.ieee.org/ielx7/8100276/8103992/08104027.pdf?arnumber=8104027","host_type":"publisher"},{"url":"https://doi.org/10.1109/acsd.2017.14","host_type":""}],"fields_of_study":["Low-power high-performance VLSI design","VLSI and FPGA Design Techniques","Formal Methods in Verification"],"mesh_terms":[],"keywords":["Asynchronous communication","Computer science","Asynchronous system","Electronic circuit","Asynchronous circuit","Computer architecture","Interface (matter)","Theoretical computer science","Clock signal","Synchronous circuit","Parallel computing","Computer network","Electrical engineering","Telecommunications","Engineering"],"sdg_mappings":[{"sdg_number":0,"sdg_label":"Industry, innovation and infrastructure"}],"linked_datasets":[],"clinical_trials":[],"software_tools":[],"database_accessions":[],"source":"live","citation_network_status":"fetched"},"created_at":"2026-08-18T22:41:59.490223Z","pmid":null,"pmcid":null,"fwci":null,"citation_percentile":null,"influential_citations":0,"oa_status":null,"license":null,"views":0,"total_file_size_bytes":0,"version_count":0,"fair_f":null,"fair_a":null,"fair_i":null,"fair_r":null,"fair_zscore":null,"fair_rationale":null,"fair_model":null,"fair_agent_version":null,"fair_fulltext_source":null,"fair_has_llm":null,"fair_computed_at":null,"clinical_trials":[],"software_tools":[],"db_accessions":[],"linked_datasets":[],"topics":[]}